library verilog;
use verilog.vl_types.all;
entity mod_sync_gen is
    generic(
        freq_p          : integer := 100000000
    );
    port(
        reset_n         : in     vl_logic;
        clk             : in     vl_logic;
        start           : in     vl_logic;
        vldata_o        : out    vl_logic;
        vrdata_o        : out    vl_logic;
        vhdata_o        : out    vl_logic;
        vlsync_o        : out    vl_logic;
        vrsync_o        : out    vl_logic;
        vhsync_o        : out    vl_logic;
        vsample_o       : out    vl_logic;
        vclamp_o        : out    vl_logic;
        data_param      : in     vl_logic_vector(31 downto 0);
        addr_param      : out    vl_logic_vector(31 downto 0);
        addr_image      : out    vl_logic_vector(31 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of freq_p : constant is 1;
end mod_sync_gen;
